A Method for Determining Trap Distributions of Specific Channel Surfaces in InGaAs Tri-gate MOSFETs
We present a method for estimating the trap distributions on each of the surfaces in a multi-gate MOSFET. We perform I-V hysteresis measurements on InGaAs Tri-gate MOSFETs with various channel widths (25, 60 and 100 nm) from which top surface and side wall trap distributions are determined. We show that the total trap distribution of a device can be expressed as a linear combination of the top sur
